• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    A method for producing a microelectronic device having different stress zones in the surface layer of a semiconductor-on-insulator type substrate comprising amorphizing a region of the surface layer and then a lateral recrystallization of said region from zones crystalline contiguous to this region.
    公开号:FR3014244A1
    申请号:FR1361838
    申请日:2013-11-29
    公开日:2015-06-05
    发明作者:Shay Reboh；Yves Morand；Hubert Moriceau
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics SA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND STATE OF THE PRIOR ART This description relates to the field of structures formed of a semiconductor-on-insulator type substrate, and more particularly that of devices. having a semiconductor layer having deformation or mechanical stress and which is disposed on an insulating material. By mechanical deformation is meant a material which has its parameter (s) elongated crystal (s) or shortened (s).
    [0002] In the case where the deformed mesh parameter is larger than the so-called "natural" parameter of the crystalline material, it is said to be in tensive deformation or in tension. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be compressive deformation or compression. To these states of mechanical deformation, one associates states of mechanical stresses. However, it is also common to refer to these deformation states as mechanical stress states. In the remainder of the present application, this notion of strain ("strain" in the English terminology) will be generically referred to as "constraint". For certain applications, in particular for producing transistors, it may be advantageous to provide a layer of constrained semiconductor material. A mechanical stress in tension or in compression on a semiconductor layer makes it possible to induce an increase in the speed of the charge carriers, thus improving the performance of transistor devices formed in such a layer. A semiconductor-on-insulator substrate is commonly formed of a support layer covered by, and in contact with, an insulating layer, itself covered by, and in contact with, a semiconducting surface layer generally intended for serve as active layer that is to say in which at least a portion of electronic components such as transistors is intended to be formed. It is known to produce substrates of semiconductor type constrained on insulator, that is to say in which the material of the semiconducting surface layer resting on the insulating layer is based on a constrained material. It is known for example to make sS01 (sS01) substrates for "strained Silicon On Insulator" (silicon on insulator) having a surface layer of voltage-constrained silicon, in which N-type transistors having improved performance can be formed. Such a layer is, however, unfavorable for the production of P-type transistors. It is also known to produce devices in which on the same support one or more transistors are voltage-stressed while one or more transistors are constrained in compression.
    [0003] The document US 2008/0124858 A1 for example provides a method in which an NMOS-type transistor and a PMOS-type transistor are formed on the same semiconductor-on-insulator substrate from a semiconductor voltage-stressed layer. In this method, after making the transistors, zones of this semiconductor layer disposed on either side of a channel region of the PMOS transistor are rendered amorphous by performing a localized implantation of a portion of the semi-conducting layer. and then recrystallizing this portion in order to release the constraint for the PMOS transistor. The amorphous implantation step may tend to induce dislocations in the transistors.
    [0004] Moreover, when recrystallization is carried out after fabrication of the transistors, the management of the thermal budget required can be restrictive. In addition, because of the presence of the gate stack, it may be difficult to obtain an effective relaxation of the mechanical stresses of the channel region of the transistor.
    [0005] There is the problem of finding a new method of implementation for the implementation on the same semiconductor-on-insulator substrate of semiconductor zones having different constraints, and which does not have the drawbacks mentioned above. .
    [0006] PRESENTATION OF THE INVENTION The present invention relates, according to one aspect, to a method comprising, on a substrate of semiconductor type constrained on insulator provided with a support layer, an insulating layer, and a surface layer based on of crystalline constrained semiconductor material disposed on said insulating layer, steps of: a) rendering amorphous at least one region of said semiconductor material of said surface layer, while maintaining the crystalline structure of at least one zone of said surface layer of constrained semiconductor material contiguous to said region, b) recrystallizing said region using at least one side face of said area of crystalline constrained semiconductor material in contact with said region as a starting area of a recrystallization front. Thus, according to the invention, it is possible to produce a semiconductor-on-insulator substrate, the surface layer of which comprises stressed zones and at least one region which is relaxed from the mechanical stresses. From this substrate, components such as transistors can then be formed. The realization of the relaxed region is carried out prior to the formation of components, which in particular makes it possible to better relax the mechanical stresses of said region of the surface layer while avoiding an additional annealing step or imperatives in terms of thermal budget. during the manufacture of the component (s). The amorphization in step a) can be carried out by ion implantation.
    [0007] In this case, step b) of recrystallization may comprise at least one heat treatment. Alternatively, the amorphization in step a) and the recrystallization in step b) can be performed by means of a laser.
    [0008] Advantageously, the amorphization step a) can be carried out over the entire thickness of said region of the surface layer. An amorphization of a region of the superficial layer over its entire thickness until it reaches the insulating layer of the substrate makes it possible to obtain a relaxed region of the mechanical stresses after recrystallization.
    [0009] According to a first possibility of implementing the method, the constrained semiconductor material may be voltage-constrained silicon. Advantageously, after step b) of recrystallization, a Germanium enrichment step of said region can be carried out. This may make it possible to produce a semiconductor-on-insulator substrate whose surface layer comprises at least one region that is constrained in compression. From a substrate obtained according to this first implementation possibility, it is then possible to form a microelectronic transistor device provided with at least one P-type transistor, in particular PFET or PMOS transistor, and at least one transistor transistor. type N, in particular NFET or NMOS, said region relaxed or constrained in compression in a plane parallel to the main plane of the substrate, being intended to form a channel region for said transistor N, said voltage-stressed zone in said plane being intended for forming a channel region for said transistor P. Alternatively, according to a second possibility of implementing the method, said constrained semiconductor material may be silicon germanium (SixGel_x with 0 x 1) constrained in compression. The constrained germanium silicon in compression can be advantageously obtained prior to step a), by enriching in Ge a Si layer resting on said insulating layer. From a substrate obtained according to this second implementation possibility, it is then possible to form a microelectronic transistor device provided with at least one N-type transistor, in particular NFET or NMOS, and at least one transistor of type P, in particular PFET or PMOS, said region being intended to form a channel region for said transistor P, said zone being intended to form a channel region for said transistor N.
    [0010] According to one possibility of implementing the method, it is possible to carry out a partial recrystallization of said region so as to maintain an amorphous portion in said region at the end of the recrystallization. According to a possibility of implementing the method, the region rendered amorphous in step a) and recrystallized in step b) may comprise a first lateral face contiguous to the crystalline zone of said superficial layer and at least one second lateral face. which is not in contact with an area of crystalline material. Advantageously, the other side faces of the amorphous region are not in contact with an area of crystalline material. In this case, it is possible to form a lateral recrystallization front propagating in a single direction during recrystallization. The invention also relates to a device implemented using a previously defined method. The invention also relates to an insulator-based semiconductor substrate having a support layer, an insulating layer, a surface layer based on a semiconductor material, an area of said surface layer resting on a said insulating layer being based on a constrained crystalline semiconductor material, a region of said surface layer also resting on said insulating layer and adjoining said zone being based on relaxed crystalline semiconductor material or based on compression-stressed material; .
    [0011] The invention also relates to a transistor device comprising such a substrate.
    [0012] BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIGS. 1A-1E illustrate a method of producing a constrained semiconductor-on-insulator substrate having a generally voltage-constrained semiconductive surface layer and having at least one region in which this stress is relaxed; FIG. 2 illustrates a transistor device formed on the substrate of FIG. 1E and in which an N-type transistor channel is formed in the voltage-constrained semiconductor layer and a P-type transistor channel is formed in a relaxed region of the semiconductor layer; FIGS. 3A-3C illustrate a method of producing a substrate of semiconductor type constrained on insulator having a semiconductive superficial layer generally constrained in compression and comprising at least one region in which this stress is relaxed; FIG. 4 illustrates a transistor device formed on the substrate of FIG. 3C and in which an N-type transistor channel is formed in the relaxed semiconductor layer and a P-type transistor channel is formed in said compression-constrained region. ; FIGS. 5A-5C illustrate a Germanium enrichment of a relaxed region of a voltage-on-insulator semiconductor layer in order to form a substrate provided with at least one compression-on-insulator stressed region and at least one semiconductor zone stressed in tension on insulator; FIG. 6 illustrates a transistor device formed from the substrate of FIG. 5C and in which an N-type transistor channel is formed in a voltage-constrained semiconductor layer and a P-type transistor channel is formed in a region enriched in Germanium of this layer and compressive stress; FIGS. 7A-7B illustrate a variant of the exemplary method of FIGS. 1A-1B in which localized amorphization and lateral recrystallization steps are performed using a laser; FIGS. 8A-8B illustrate an embodiment variant in which a localized amorphization and then a lateral recrystallization of a semiconductor region are carried out, the recrystallization of this region being partial so as to maintain an amorphous portion; FIG. 9 illustrates an alternative embodiment of a process according to the invention in which a recrystallization of an amorphous semiconducting region partially surrounded by an area of crystalline semiconductor material is carried out; FIG. 10 illustrates an alternative embodiment of a process according to the invention in which a recrystallization of an amorphous semi-conductor region provided with a high aspect ratio is carried out in order to limit the areas of contact between recrystallization fronts in the region. propagating in different directions; FIG. 11 illustrates an alternative embodiment of a process according to the invention in which a recrystallization of an amorphous semiconductor region is carried out, one of whose lateral faces is contiguous with an area of crystalline material, and its other lateral faces. not being contiguous to a crystalline material to create a recrystallization front propagating in a single direction; Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    [0013] In addition, in the description below, terms that depend on the orientation of the structure apply considering that the structure is oriented as illustrated in the figures.
    [0014] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS An exemplary method according to the invention will now be described with reference to FIGS. 1A-1E. The starting material of this process is a semiconductor substrate constrained on insulator, for example of the sS01 type, comprising a superficial semiconductor layer 13, on and in contact with an insulating layer 12 which may be based on silicon oxide and which is arranged on and in contact with the support layer 11. The insulating layer 12 may have a thickness for example between 10 nm and 100 nm.
    [0015] The substrate comprises the superficial semiconductor layer 13, in this Si-based example, which is constrained and located on and in contact with said insulating layer 12. This semiconducting surface layer 13 can be voltage-stressed and have a thickness for example between 5 nm and 50 nm. A masking 20, which may for example be based on photosensitive polymer, is then formed on one or more zones 13a of the semiconductive superficial layer 13, while at least one region 13b juxtaposed with the zones 13a covered by the masking 20 is unveiled. Channels of transistors of a first type, in particular N type, may be intended to be made in the zones 13a of the semiconducting surface layer 13 covered by the masking 20. In the region 13b which is not covered by masking 20, at least one transistor channel of a second type, for example of type P, may be designed to be formed. Through an opening 21 of the masking 20, an ion implantation is then carried out, so as to render the region 13b of the semiconducting surface layer 13 amorphous, while the zones 13a protected by the masking 20 are not implanted and thus retain their crystalline structure (Figure 1B). In the particular example of FIG. 1B, the region 13b is advantageously made amorphous over its entire thickness e (measured in a z direction of an orthogonal reference [O; x; y; z] in FIG. 1B). that is, to the insulating layer 12 of the substrate. The amorphizing implantation can be carried out for example based on Ge, or Si, or As, or C, or Ar, or N atoms, at an energy chosen according to the nature of the species. implanted and the nature and thickness of the semiconductor surface layer 13. The implantation energy may be for example between 3 keV and 40 keV, and the implantation dose is for example between 1014 and 5 x 1015 atoms / cm2.
    [0016] For example, to amorphize a thickness of 15 nm of Si, Si ions can be implanted at an energy of between 6 keV and 8 keV at a dose of between 4 × 10 14 and 1 × 10 15 atoms / cm 2. To amorphize a thickness of 30 nm of Si, Si ions can be implanted at an energy of between 14 keV and 25 keV at a dose of the order of 5 x 10 14 atoms / cm 2. Then, the masking is removed and recrystallization of the amorphous region 13b is carried out, using side faces 15a, 16a of zones 13a adjoining and contiguous to region 13b as starting zones of the recrystallization fronts ( Figure 1C). The lateral faces 15a, 16a extend in the example of FIG. 1C parallel to an axis z of an orthogonal reference [0, x, y, z]. The starting zones at the recrystallization fronts are thus not parallel to the main plane of the substrate (defined here and throughout the description as a plane passing through the substrate and parallel to the plane [0, x, y] given in FIG. 1C) , but realize a non-zero angle with the main plane of the substrate. In the particular example of FIG. 1C, the region 13b is contiguous with several crystalline zones 13a. To carry out the recrystallization, annealing is carried out at a temperature of, for example, between 500 ° C. and 1100 ° C., for a duration of, for example, between 1 s and 30 min. Crystalline seeds are grown laterally from the periphery of the region 13b towards its center, the recrystallization fronts moving horizontally, ie parallel to the main plane of the substrate (FIG. 1D).
    [0017] Thus, at the end of this so-called "lateral" recrystallization, a semiconductor-on-insulator substrate of which the superficial semiconductor layer intended to serve as an active layer has zones 13a of constrained semiconductor material, here constrained silicon, disposed on either side and adjacent to a recrystallized semiconductor region 13b which is relaxed (FIG. 1E). Then, components, in particular transistors, can be formed from the zones 13a and 13b of the substrate. Transistor channels T11, T12 of the NFET type may be provided in the zones 13a of the semiconductor surface layer 13 in which the voltage stress has been maintained, while at least one PFET type transistor channel T21 may be expected in the relaxed region 13b (Figure 2). According to a variant of the example of the method which has just been described, it is possible to choose as a starting material a semiconductor-type constrained on insulator of another type, for example of the type sSiGe01 (sSiGe01 for "strained Silicon germanium on insulator "or" silicon germanium constrained on insulator ") formed of a semiconductor carrier layer 11, an insulating layer 12, and a semiconductor surface layer 14 based on SixGel_x (with 0 1), compressive stress in the plane, and disposed on and in contact with the insulating layer 12. The semiconductor surface layer 14 based on SixGel_x can be obtained by Ge enrichment of a silicon layer. The Germanium enrichment of the silicon layer may be carried out, for example, using a technique known as "Germanium condensation" as described for example in the document "Fabrication of strained Si on an ultrathin SiGe on Insulator virtual substrate". with a high Ge fraction, Appl. Phys. Lett. 79, 1798, 2001, by Tezuka et al. or in the document "The technical condensation: a solution for planar SOI / Ge01 co-integration for advanced CMOS technologies", Materials Science in Semiconductor Processing 11 (2008) 205-213, Damlencourt et al. The germanium condensation may consist, for example, of depositing a layer of SixGel_x on an Si layer of an SOI substrate, then oxidizing these semiconductor layers in such a way as to migrate the Germanium into the underlying Si layer and then removing the oxidized surface layer. A planarization of the SixGel_x layer thus obtained, for example by CMP (CMP for "Chemical Mechanical Polishing" or "chemical mechanical polishing") can then be performed. Masking 20 is then formed on areas 14a of SixGel_x semiconductor surface layer 14, while at least one region 14b is exposed by an opening in masking 20 (FIG. 3A). At least one channel of a P-type transistor is intended to be formed in areas 14a of the semiconductor surface layer of SixGel_x, while at least one N-type transistor channel is intended to be realized in the region 14b which is not covered by the masking 20. Then, the region 14b of the semi-conducting surface layer 14 exposed by the opening 21 of the mask 20 is made amorphous, for example by means of a beam of ion or laser (Figure 3B). The amorphization and the recrystallization cause a relaxation of the stress exerted on the 14b region based on SiGe, while the zones 14a which are bordering on the region 14b and which have not been implanted retain their stress. A recrystallization annealing of the region 14b is then carried out by using, on the lateral faces 14a1, 14a2, crystalline zones 14a arranged on either side and contiguous to the region 14b as starting zones at lateral recrystallization fronts ( Figure 3C). Masking 20 can then be removed. Then PMOS type transistors T22, T23 are produced from the zones 14a of the SiGe-based semiconductor surface layer 14, or the compression in the plane has been preserved, whereas an NMOS-type transistor T13 is produced. from region 14b (Figure 4). Transistors T22, T23 thus have a channel located in zones 14a constrained in compression, while transistor T13 has a channel located in a relaxed region 14b semiconductor. It is also possible to produce a substrate on insulator whose superficial semiconductor layer comprises one or more semiconductor zones constrained according to a first type of stress, for example in tension, and one or more semiconductor regions constrained according to a second type of stress, for example in compression, from a substrate as described above in connection with Figure 1E. For this, on the surface of the semiconductor layer 13 of tension-stressed silicon, a mask 50 for protecting the oxidation is first formed, comprising at least one opening 51 revealing said region 13b based on Si and whose stress was relaxed. This mask 50 may be based on silicon nitride SiN or Si3N4 and covers the areas 13a of the superconducting semiconductor layer 13 whose voltage stress has been preserved (FIG. 5A).
    [0018] In this opening 51 of the mask 50, a layer 52 based on SiGe or Sii_xGex is deposited on the relaxed region 13a. The region 13b is then enriched by oxidation through the opening 51 of the mask 50, the latter protecting the zones 13a from this oxidation.
    [0019] As shown in FIG. 5B, a transformation of the stack formed of the region 13b and of the SiGe layer 52 into a block 53 of SixGel is obtained, resting on the insulating layer 12 of the substrate 10. The enrichment can be such that the block 53 is entirely made of germanium (x being equal to 0). The block 53 formed is then covered with a layer of silicon oxide 54, which is then removed, as well as the oxidation mask (FIG. 5C). The mask 50 can be removed for example by means of an H 3 PO 4 solution or by dry etching, whereas that of the silicon oxide layer can be carried out for example using HF. A substrate having a SiGe or germanium block 53 is thus obtained on the insulating layer 12 of the substrate, which may be constrained in compression, and stress-stressed zones 13a of Si on this same insulating layer 12 of the substrate. A planarization, in order to put the block 53 enriched in Germanium at the same level as the zones 13a, 13b of constrained silicon can then be performed.
    [0020] Transistors T31, T32 of the NFET type can then be formed on the zones 13a of the semiconductor surface layer 13, while a PFET type transistor T41 can be produced on the Ge-enriched block 53 (FIG. 6). . NFET type transistors T31, T32 thus have a channel located in voltage-stressed zones 13a, while transistor T41 has a channel located in a region 53 constrained in compression. According to an alternative embodiment of one or the other of the examples of the process which have just been described, it is possible to carry out the step of amorphizing a region 13b of the surface layer of a substrate using a laser beam 70 (FIG. 7A).
    [0021] In this case, a masking 80 comprising or covered with a reflective coating formed for example of a stack of several layers whose index and thickness are adapted according to the wavelength of the laser to reflect the radiation laser and protect from this radiation the semiconductor zones 13a that we do not wish to amorphize.
    [0022] According to another possible embodiment of the masking, it may be formed of a layer of sufficient thickness to allow to absorb or dissipate the laser radiation and prevent amorphization. The laser used may be for example a XeCI laser whose power may be for example between 100 mJ / cm 2 and 400 mJ / cm 2 excimer or a ruby laser. The laser radiation can be applied in the form of pulses of duration of for example between 2.5 ns and 100 ns. The step of recrystallization of the region 13b made amorphous, using side faces 15a, 16a adjacent areas 13a, and contiguous against the region 13b, as starting areas at recrystallization fronts, is then performed by the same laser. According to a variant (FIGS. 8A-8B) of realization of the process described above in connection with FIGS. 1A-1E, it can be sought to recrystallize only partially the amorphous region 13b so as to keep an amorphous portion 33 in the surface layer 13 at the same time. result of the step of lateral recrystallization.
    [0023] Thus, the lateral faces 15a, 16a of the crystalline zones 13a disposed on either side and placed against the amorphous region 13b as starting zones at lateral recrystallization fronts are used, but this recrystallization of the amorphous region 13b is in this example carried out according to a determined duration of the recrystallization heat treatment provided sufficiently short to allow to keep an amorphous portion 33 in the region 13b. When the lateral recrystallization is carried out by thermal annealing from a structure as illustrated in FIG. 8A, at a given annealing temperature, the duration of this annealing is adjusted sufficiently short for recrystallization fronts to occur. lateral F1, F2 propagating from the side faces 15a, 16a do not have time to join. The lateral recrystallization process may be carried out on an amorphous region 13b which is not entirely surrounded by zones of crystalline semiconductor material, as illustrated on the respective structures of FIGS. 9, 10, 11 (the structure being shown for 10 to 11) having an amorphous region 13b provided with at least one first face 41 which is free and is in particular not contiguous to a crystalline zone, while at least one second face 42 is contiguous at a crystalline zone 13a. In the example of FIG. 10, the structure is also provided with an amorphous region 13b (shown in plan view), whose L / W shape ratio between its length L and its width W measured parallel to the plane of the substrate ( ie a plane [0, x, y] of an orthogonal reference [0, x, y, z] given in FIG. 10) is provided at least 1 so as to limit the extent of the portions of the region 13b where several lateral recrystallization fronts F1, F2 propagating in different directions are likely to meet. In the example of FIG. 11, the arrangement between the amorphous region 13b (illustrated in plan view) and the crystalline zone (s) 13a is this time provided so that a boundary 50 between the amorphous region 13b and the crystalline zone (s) 13a contiguous to this region, form a single plane providing a non-zero angle with the main plane of the substrate. This plane may for example be orthogonal or substantially orthogonal to the main plane of the substrate. The amorphous region 13b thus comprises a single lateral face 42 in contact with an area of crystalline semiconductor material, the other lateral faces 41, 43, 44 (in this example parallel to the z axis of the reference [0, x, y z) of the amorphous region not in contact with any other material or in contact with another material which is not crystalline or from which a crystallization front can not be generated. recrystallizing heat treatment of the amorphous region 13b, it is advantageous to create a recrystallization side F1 which is unique and does not have to encounter another recrystallization front.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. A method comprising steps of, from an insulator-constrained semiconductor substrate (10,100) having a carrier layer (11), an insulating layer (12) disposed on the carrier layer, and a surface layer (13, 14) based on crystalline semiconductor hard material disposed on said insulating layer: a) amorphous at least one region (13b, 14b) of said constrained semiconductor material of said surface layer (13, 14), while retaining the crystalline structure of at least one zone (13a, 14a) of said superficial layer of constrained semiconductor material contiguous to said region, b) at least partially recrystallizing said region (13b, 14b ) using at least one side face (15a, 16a, 14a1, 14a2) of said zone of constrained semiconductor material in contact with said region as a starting area of a recrystallization front.
    [0002]
    2. Method according to claim 1, wherein the surface layer has a thickness e said region rendered amorphous in step a) having a thickness equal to the thickness e.
    [0003]
    3. Method according to one of claims 1 or 2, wherein the amorphization is performed using an ion beam through a masking (20) formed on the semiconductor surface layer (13, 14). ), an opening (21) of the masking revealing said region (13b, 14b).
    [0004]
    4. Method according to one of claims 1 to 3, wherein said constrained semiconductor material is voltage-strained silicon.
    [0005]
    5. The method of claim 4, further comprising, after step b), a step of enriching germanium of said region. 25
    [0006]
    6. A method of producing a microelectronic transistor device according to one of claims 4 or 5, further comprising, after step b) of recrystallization, the embodiment of at least one P-type transistor (T21, T41). ) and at least one N-type transistor (T11, T12, T31, T32) said region being for forming a channel region for said transistor N, said area being for forming a channel region for said P transistor.
    [0007]
    7. Method according to one of claims 1 or 2, wherein said constrained semiconductor material is silicon germanium constrained in compression.
    [0008]
    8. The method of claim 7, wherein the compression-constrained silicon germanium is obtained prior to step a) by Ge enrichment of a Si layer resting on said insulating layer.
    [0009]
    9. A method of producing a microelectronic device according to one of claims 7 or 8 with transistors, further comprising, after step b) of recrystallization, the embodiment of at least one P-type transistor (T22, T23) and at least one N-type transistor (T13) said region being intended to form a channel region for said transistor P, said area being intended to form a channel region for said transistor N.
    [0010]
    10. Method according to one of claims 1 to 9, wherein step a) and step b) are performed using a laser.
    [0011]
    11. Method according to one of claims 1 to 9, wherein step b) comprises at least one thermal annealing.
    [0012]
    12. Method according to one of claims 1 to 9 and 11, wherein step b) is a partial recrystallization of said region (13b) so as to maintain at the end of step b), an amorphous portion (33) in said region.
    [0013]
    13. Method according to one of claims 1 to 12, wherein said region (13b) made amorphous in step a) and recrystallized in step b) comprises a side face (42) contiguous to said zone (13a, 14a) of said surface layer, the other side faces (41, 43, 44) of the amorphous region not being in contact with an area of crystalline material.
    [0014]
    An insulator-constrained semiconductor substrate having a support layer (11), an insulating layer (12) disposed on the support layer, a surface layer (13, 14) based on semiconductor material disposed on the insulating layer, a zone (13a, 14a) of said surface layer resting on said insulating layer being based on a constrained crystalline semiconductor material, a region (13b, 53, 14b) of said a superficial layer also resting on said insulating layer (12) and adjoining said zone being based on relaxed crystalline semiconductor material or based on compression-stressed material.
    [0015]
    A transistor device comprising a substrate according to claim 14.
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    同族专利:
    公开号 | 公开日
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1361838A|FR3014244B1|2013-11-29|2013-11-29|IMPROVED METHOD FOR PRODUCING A CONDUCTIVE SEMICONDUCTOR SUBSTRATE ON INSULATION|
    FR1361838|2013-11-29|FR1361838A| FR3014244B1|2013-11-29|2013-11-29|IMPROVED METHOD FOR PRODUCING A CONDUCTIVE SEMICONDUCTOR SUBSTRATE ON INSULATION|
    US14/555,897| US9899217B2|2013-11-29|2014-11-28|Method for producing a strained semiconductor on insulator substrate|
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